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10-Bit, 12-Channel Decimating LCD DECDRIVER(R) with Level Shifters AD8385
FEATURES
High voltage drive to within 1.3 V of supply rails Output short-circuit protection High update rates Fast, 100 Ms/s 10-bit input data update rate Static power dissipation: 1.84 W Voltage controlled video reference (brightness), offset, and full-scale (contrast) output levels INV bit reverses polarity of video signal 3.3 V logic, 9 V to 18 V analog supplies Level shifters for panel timing signals High accuracy voltage outputs Laser trimming eliminates the need for adjustments or calibration Flexible logic STSQ/XFR allow parallel AD8385 operation Fast settling into capacitive loads 30 ns settling time to 0.25% into 150 pF load Slew rate 460 V/s Available in 100-lead 14 mm x 14 mm TQFP E-pad
BYP VRH VRH VRL DB(0:9) R/L CLK STSQ XFR INV V1 V2 TSTM SDI SCL SEN SVRH SVRL SVRL DYIN DXIN DIRYIN DIRXIN NRGIN ENBX1I ENBX2I ENBX3I ENBX4I 3 3 12-BIT SHIFT REGISTER DUAL DAC VAO1 VAO2 3
FUNCTIONAL BLOCK DIAGRAM
BIAS
/ /
SCALING CONTROL 2-STAGE LATCH SEQUENCE CONTROL INV CONTROL DACs 12
10
/
4
/
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID8 VID9 VID10 VID11
/ /
9
/
9
/
GENERAL DESCRIPTION
The AD8385 provides a fast, 10-bit, latched decimating digital input that drives 12 high voltage outputs. 10-bit input words are loaded into 12 separate high speed, bipolar DACs sequentially. Flexible digital input format allows several AD8385s to be used in parallel in high resolution displays. The output signal can be adjusted for dc reference, signal inversion, and contrast for maximum flexibility. Integrated level shifters convert timing signals from a 3 V timing controller to high voltage for LCD panel timing inputs. Two, serial, 8-bit DACs are integrated to provide dc reference signals. A 3-wire serial interface controls overload protection, output mode, and the serial DACs. The AD8385 is fabricated on ADI's fast bipolar, 26 V XFHV process, which provides fast input logic, bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip. The AD8385 dissipates 1.84 W nominal static power. The AD8385 is offered in a 100-lead, 14 mm x 14 mm TQFP E-pad package and operates over the commercial temperature range of 0C to 85C.
DY DX DIRY DIRX NRG ENBX1 ENBX2 ENBX3 ENBX4 CLX CLY CLXN CLYN
2 CLXIN CLYIN 2
/
/ /
2
R MONITI S MONITO
04514-0-001
AD8385
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2005 Analog Devices, Inc. All rights reserved.
AD8385 TABLE OF CONTENTS
Specifications..................................................................................... 3 DECDRIVER Section .................................................................. 3 Level Shifters ................................................................................. 4 Level Shifting Edge Detector ...................................................... 5 Serial Interface .............................................................................. 5 Power Supplies .............................................................................. 6 Operating Temperature ............................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Overload Protection..................................................................... 8 Exposed Paddle............................................................................. 8 Maximum Power Dissipation ..................................................... 8 Operating Temperature Range ................................................... 8 Pin Configuration and Function Descriptions............................. 9 Block Diagrams and Timing Diagrams ....................................... 11 DECDRIVER Section ................................................................ 11 Level Shifters ............................................................................... 13 Level Shifting Edge Detector .................................................... 14 Serial Interface ............................................................................ 15 Functional Description .................................................................. 16 Reference and Control Input .................................................... 16 Output Operating Mode............................................................ 17 Overload Protection................................................................... 17 Serial DACs ................................................................................. 17 Theory of Operation ...................................................................... 18 Transfer Function and Analog Output Voltage ...................... 18 Accuracy ...................................................................................... 18 Applications..................................................................................... 19 Optimized Reliability with the Thermal Switch..................... 19 Operation in High Ambient Temperature .............................. 20 Power Supply Sequencing ......................................................... 20 VBIAS Generation--V1, V2 Input Pin Functionality ........... 20 Applications Circuit ................................................................... 21 PCB Design for Optimized Thermal Performance ............... 21 Thermal Pad Design .................................................................. 21 Thermal Via Structure Design.................................................. 21 AD8385 PCB Design Recommendations ............................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
1/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8385 SPECIFICATIONS
DECDRIVER SECTION
@ 25C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0C, TA MAX = 85C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted. Table 1.
Parameter VIDEO DC PERFORMANCE1 VDE VCME VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time to 1% Data Switching Settling Time to 0.25% Invert Switching Settling Time to 1% Invert Switching Settling Time to 0.25% Invert Switching Overshoot CLK and Data Feedthrough2 All-Hostile Crosstalk3 Amplitude Glitch Duration DAC Transition Glitch Energy VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage--Grounded Mode Data Switching Delay: t94 INV Switching Delay: t105 INV to CLK Setup Time: t27 Output Current Output Resistance REFERENCE INPUTS V1 Range V2 Range V1 Input Current V2 Input Current VRL Range VRH Range VRH to VRL Range VRH Input Resistance VRL Bias Current VRH Input Current RESOLUTION Coding Conditions TMIN to TMAX DAC Code 450 to 800 DAC Code 450 to 800 TMIN to TMAX , VO = 5 V step, CL = 150 pF 20% to 80% 20% to 80% Min -7.5 -3.5 460 560 19 30 75 250 100 10 10 30 0.3 1.1 0.25 12 15 100 22 V2 (V1 - 0.25 V) V2 (V1 - 0.25 V) 5 5 -5 -27 VRH VRL VRH VRL VFS =2 x (VRH - VRL) To VRL V1 - 0.5 VRL 0 20 -0.2 125 10 AVCC - 1.3 AVCC 2.75 AVCC - 4 AVCC - 4 1.3 14 17 5.5 fCLK Typ Max +7.5 +3.5 Unit mV mV V/s V/s ns ns ns ns mV mV p-p mV p-p ns nV-s V V ns ns ns mA V V A A V V V k A A Bits
24 50 120 500 200
DAC Code 511 to 512 AVCC - VOH, VOL - AGND 50 % of VIDx 50 % of VIDx 10 13 0.5 fCLK
Binary
Rev. 0 | Page 3 of 24
AD8385
Parameter DIGITAL INPUT CHARACTERISTICS Max. Input Data Update Rate Data Setup Time: t1 STSQ Setup Time: t3 XFR Setup Time: t5 Data Hold Time: t2 STSQ Hold Time: t4 XFR Hold Time: t6 CLK High Time: t7 CLK Low Time: t8 CIN IIH IIL VIH VIL VTH Conditions Input tr, tf = 2 ns Min 100 0 0 0 3 3 3 3 2.5 3 0.05 -0.6 2 0.8 1.65 Typ Max Unit Ms/s ns ns ns ns ns ns ns ns pF A A V V V
1 2
VDE = differential error voltage; VCME = common-mode error voltage; VFS = full-scale output voltage = 2 x (VRH - VRL). See the Accuracy section. Measured on two outputs differentially as CLK and DB(0:9) are driven and XFR is held low. 3 Measured on two outputs differentially as the other four are transitioning by 5 V. Measured for both states of INV. 4 Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV. 5 Measured from 50% of rising CLK edge that follows a valid XFR to 50% of output change. Refer to Figure 6 for the definition.
LEVEL SHIFTERS
@ 25C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0C, TA MAX = 85C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted. Table 2.
Parameter LEVEL SHIFTER LOGIC INPUTS CIN IIH IIL VTH VIH VIL LEVEL SHIFTER OUTPUTS VOH VOL LEVEL SHIFTER DYNAMIC PERFORMANCE Output Rise, Fall Times--tr, tf DX, CLX, CLXN, ENBX[1-4] DY, CLY, CLYN DIRX, DIRY NRG NRG Propagation Delay Times--t11, t12, t13, t14 DX, CLX, CLXN, ENBX[1-4] DY, CLY, CLYN DIRX, DIRY NRG NRG Output Skew ENBX[1-4]--t15, t16 DX to ENBX[1-4]--t16 DX to CLX--t15, t16, t17, t18 DY, CLY, CLYN--t15, t16, t17, t18 Conditions Min Typ Max 3 2 Unit pF A A V V V V V
-2 2.0 DGND RL > 10 k
0.05 -0.6 1.65
DVCC 0.8 AVCC - 0.25 0.25
TA MIN to TA MAX CL = 40 pF CL = 40 pF CL = 40 pF CL = 200 pF CL = 300 pF CL = 40 pF CL = 40 pF CL = 40 pF CL = 200 pF CL = 300 pF CL = 40 pF CL = 40 pF CL = 40 pF CL = 40 pF
Rev. 0 | Page 4 of 24
18.5 40 102 43 61 20 29 70 30 37
30 70 200 50 100 50 50 100 100
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2 2 10 20
AD8385
LEVEL SHIFTING EDGE DETECTOR
@ 25C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0C, TA MAX = 85C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted. Table 3.
Parameter VIL VIH VTH LH VTH HL VOH VOL IIH IIL t19 t19 t20 t20 tr tf Conditions Input Low Voltage Input High Voltage Input Rising Edge Threshold Voltage Input Falling Edge Threshold Voltage Output High Voltage Output Low Voltage Input Current High State Input Current Low State Input Rising Edge Propagation Delay Time t19 Variation with Temperature Input Falling Edge Propagation Delay Time t20 Variation with Temperature Output Rise Time Output Fall Time Min AGND AVCC - 0.7 Typ Max AGND + 0.75 AVCC Unit V V V V V V A A ns ns ns ns ns ns
-2.5 CL = 10 pF CL = 10 pF 10% to 90% 10% to 90%
AGND + 1 AVCC - 1 DVCC - 0.25 0.25 1.2 -1.2 16 2 12 2 5 6
2.5
SERIAL INTERFACE
@ 25 C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0C, TA MAX = 85C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted. Table 4.
Parameter SERIAL DAC REFERENCE INPUTS SVRH Range SVRL Range SVFS Range SVRH Input Current SVRL Input Current SVRH Input Resistance SERIAL DAC ACCURACY DNL INL Output Offset Error Scale Factor Error SERIAL DAC LOGIC INPUTS CIN IIN LOW Low Level Input Current IIN HIGH High Level Input Current VTH Input Threshold Voltage VIH Input High Voltage VIL Input Low Voltage SERIAL DAC OUTPUTS Maximum Output Voltage Minimum Output Voltage VAO1--Grounded Mode IOUT CLOAD Low Range1 CLOAD High Range1 Conditions SVFS = (SVRH - SVRL) SVRL SVRH SVRL SVRH SVFS = 5 V SVFS = 5 V Min SVRL + 1 AGND + 1.5 1 -2.8 125 -2.5 40 Typ Max AVCC - 3.5 SVRH - 1 8 150 Unit V V V A mA k LSB LSB LSB LSB pF A A V V V V V V mA F F
SVFS = 5 V, RL = SVFS = 5 V, RL =
-1.0 -1.5 -2.0 -3
+1.0 +1.5 +2.0 +3 3 -0.6 0.05 1.65
Input tr, tf = 10 ns
2.0 DGND SVRH - 1 LSB SVRL 0.1 30
DVCC 0.8
0.002 0.047
Rev. 0 | Page 5 of 24
AD8385
Parameter SERIAL INTERFACE DYNAMIC PERFORMANCE SEN to SCL Setup Time, t20 SCL, High Level Pulse Width, t21 SCL, Low Level Pulse Width, t22 SDI Setup Time, t24 SDI Hold Time, t25 SCL to SEN Hold Time, t23 VAO1, VAO2 Settling Time, t26 VAO1, VAO2 Settling Time, t26 Conditions Min 10 10 10 10 10 10 SVFS = 5 V, to 0.5%, CL = 100 pF SVFS = 5 V, to 0.5%, CL = 33 F 1 2 15 Typ Max Unit ns ns ns ns ns ns ms ms
1
Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. For proper operation of these outputs, load capacitance must be 0.002 F or 0.047 F. Load capacitance in the range of 0.002 F to 0.047 F causes the output overshoot to exceed 100 mV.
POWER SUPPLIES
@ 25C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0C, TA MAX = 85C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted. Table 5.
AD8385 Power Supplies DVCC, Operating Range DVCC, Quiescent Current AVCC Operating Range Total AVCC Quiescent Current Min 3 9 111 Typ 3.3 56 Max 3.6 18 Unit V mA V mA
OPERATING TEMPERATURE
@ 25C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0C, TA MAX = 85C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted. Table 6.
Parameter Ambient Temperature Range, TA1 Ambient Temperature Range, TA2 Min 0 0 Typ Max 75 85 Unit C C
1
Operation at high ambient temperature requires a thermally-optimized PCB layout (see the Applications section), input data update rate not exceeding 85 MHz, blackto-white transition 4 V and CL 150 pF. In systems with limited or no airflow, the maximum ambient operating temperature is limited to 75C with the overload protection enabled. For operation above 75C, see Endnote 2. 2 In addition to the requirements stated in Endnote 1, operation at 85C ambient temperature requires 200 lfm airflow or the overload protection disabled.
Rev. 0 | Page 6 of 24
AD8385 ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Supply Voltage AVCCx - AGNDx DVCC - DGND Input Voltage Maximum Digital Input Voltage Minimum Digital Input Voltage Maximum Analog Input Voltage Minimum Analog Input Voltage Internal Power Dissipation1 TQFP E-Pad Package @ TA = 25C Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering, 10 sec) Rating 18 V 4.5 V DVCC + 0.5 V DGND - 0.5 V AVCC + 0.5 V AGND - 0.5 V 5.00 W 0C to 85C -65C to 125C 300C
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability.
1
100-lead TQFP E-pad package: JA = 20C/W (still air), JEDEC STD, 4-layer PCB in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 24
AD8385
OVERLOAD PROTECTION
The AD8385 employs a 2-stage overload protection circuit with an enable/disable function that is programmable through the 3-wire serial interface. It consists of an output current limiter and a thermal shut down. When enabled, the maximum current at any one output of the AD8385 is, on average, internally limited to 100 mA. In the event of a momentary short circuit between a video output and a power supply rail (VCC or AGND), the output current limit is sufficiently low to provide temporary protection. The thermal shutdown debiases the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typ, with a period determined by the thermal time constant and the hysteresis of the thermal trip point. Thermal shutdown provides long-term protection by limiting the average junction temperature to a safe level. When disabled, no overload protection is present.
OPERATING TEMPERATURE RANGE
The maximum operating junction temperature is 150C. The junction temperature trip point of the overload protection is 165C. Production test guarantees a minimum junction temperature trip point of 125C. Consequently, the maximum guaranteed operating junction temperature is 125C with the overload protection enabled, and 150C with the overload protection disabled. To ensure operation within the specified operating temperature range, the maximum power dissipation must be limited:
PDMAX
3.0
(T
JMAX
- TA )
( JA - 0.9 x 3 Airflow in lfm )
MAXIMUM POWER DISSIPATION (W)
STILL AIR 100MHz 2.5 200 lfm 60Hz XGA 500 lfm 2.0 QUIESCENT
EXPOSED PADDLE
To ensure optimal thermal performance, the exposed paddle must be electrically connected to an external plane such as AVCC or GND, as described in the Applications Circuit section.
MAXIMUM POWER DISSIPATION
The junction temperature limits the maximum power that can be safely dissipated by the AD8385. The maximum safe junction temperature for plastic encapsulated devices, determined by the glass transition temperature of the plastic, is approximately 150C. Exceeding this limit can cause a temporary shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure.
*OVERLOAD PROTECTION ENABLED **OVERLOAD PROTECTION DISABLED 70 95 75 100 80 105 85 110 90 115 95 120 100 125 105 130
04514-0-002
1.5 *65 **90
AMBIENT TEMPERATURE (C)
AD8385 on a 4-layer JEDEC PCB with a thermally optimized landing pattern, as described in the Applications Circuit section.
Figure 2. Maximum Power Dissipation vs. Temperature
Note that the quiescent power dissipation of the AD8385 is 1.84 W when operating under the conditions specified in this data sheet. When driving a 12-channel XGA panel with an input capacitance of 150 pF, the AD8385 dissipates a total of 2.3 W when displaying 1 pixel wide alternating white and black vertical lines generated by a standard 60 Hz XGA input video. When the frequency of the pixel clock is raised to 100 MHz, the total power dissipation increases to 2.54 W. These specific power dissipations are shown in Figure 2 for reference.
Rev. 0 | Page 8 of 24
AD8385 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC NC AGNDD AVCCD STSQ XFR VRH VRH VRL V2 CLK DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 INV R/L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DVCC 1 DGND 2 SDI 3 SEN 4 SCL 5 BYP 6 TSTM 7 AGNDS 8 AGNDS 9 SVRL 10 SVRL 11 SVRH 12 VAO1 13 VAO2 14 AVCCS 15 NC 16 DIRX 17 DIRY 18 DY 19 CLY 20 CLYN 21 DIRXIN 22 DIRYIN 23 DYIN 24 CLYIN 25
NC
75 AGND0 74 VID0 73 AVCC0,2 72 VID2 71 AGND2,4 70 VID4 69 AVCC4,6 68 VID6 67 AGND6,8 66 VID8 65 AVCC8,10 64 VID10 63 AGND10,1 62 VID1 61 AVCC1,3 60 VID3 59 AGND3,5 58 VID5 57 AVCC5,7 56 VID7 55 AGND7,9 54 VID9 53 AVCC9,11 52 VID11 51 AGND11
PIN 1 IDENTIFIER
AD8385
TOP VIEW (Not to Scale) 100L 14mm x 14mm TQFP E-PAD
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ENBX2I ENBX3I
ENBX1I
ENBX4I
ENBX1 ENBX2
ENBX3
AVCCL NRGIN
MONITO DXIN
ENBX4
CLXIN DX
CLXN NC
NC
TSTA
V1 DGND
AGNDL
MONITI
DGND
DVCC
NRG
CLX
NC = NO CONNECT
Figure 3. 100-Lead TQFP Package
Table 8. Pin Function Descriptions
Pin Name DB(0:9) CLK STSQ R/L XFR VID0-VID11 V1, V2 VRH, VRL INV DVCC DGND AVCCx AGNDx BYP SVRH, SVRL Function Data Input Clock Start Sequence Right/Left Select Data Transfer Analog Outputs Reference Voltages Full-Scale References Invert Digital Power Supply Digital Ground Analog Power Supplies Analog Ground Bypass Serial DAC Reference Voltages Description 10-Bit Data Input. MSB = DB9. Clock Input. Data is acquired on both edges of the CLK. A new data loading sequence begins on the rising edge of CLK when this input was high on the preceding rising edge of CLK. A new data loading sequence begins on the left, with Channel 0, when this input is low; a new data loading sequence begins on the right, with Channel 11 when this input is high. Data is transferred to the video outputs on the next rising edge of CLK when this input is high on the rising edge of CLK. These pins are directly connected to the analog inputs of the LCD panel. The voltage applied between V1 and AGND sets the white video level during INV = low. The voltage applied between V2 and AGND sets the white video level during INV = high. The voltage applied between these pins sets the full-scale video output voltage. When this input is high, the analog output voltages are above V2. When low, the analog outputs voltages are below V1. Digital Power Supply. This pin is normally connected to the digital ground plane. Analog Power Supplies. Analog Supply Returns. A 0.1 F capacitor connected between this pin and AGND ensures optimum settling time. Reference Voltages for the Output Amplifiers of the Serial DACs.
Rev. 0 | Page 9 of 24
04514-0-003
AD8385
Pin Name SCL SDI Function Serial Interface Data Clock Serial Interface Data Input Serial Interface Enable Serial DAC Voltage Output Test Mode Description Clock for the Serial Interface. While the SEN input is low, one 12-bit serial word is loaded into the serial interface on the rising edges of SCL. The first four bits select the function; the following eight bits are the data used in the serial DACs. A falling edge of this input initiates a loading cycle. While this input is held low, the serial interface is enabled and data is loaded on every rising edge of SCL. The selected functions are updated on the rising edge of this input. While this input is held high, the serial interface is disabled. These output voltages are updated on the rising edge of the SEN input. When this input is low, the overload protection and output mode are determined by the function programmed into the serial interface. While this input is held high, the overload protection is forced to enabled and the output mode is forced to normal, regardless of function programmed into the serial interface. Connect this pin to DGND. Logic Input of the Level Shifting Inverting Edge Detector. Output of the Level Shifting Inverting Edge Detector. Logic Input of the Inverting Level Shifters.
SEN
VAO1, VAO2 TSTM
TSTA MONITI MONITO DYIN, DIRYIN, DIRXIN, DXIN, NRGIN, ENBX(1-4)IN DX, DY, DIRX, DIRY, NRG, ENBX(1-4) CLXIN, CLYIN CLX, CLXN, CLY, CLYN,
Test Pin Monitor Input Monitor Output Inverting Level Shifter Inputs
Inverting Level Shifter Outputs Complementary Level Shifter Inputs Complementary Level Shifter Outputs
While the corresponding input voltage of these level shifters is below the threshold voltage, the output voltage at these pins is at VOH. While the corresponding input voltage of these level shifters is above the threshold voltage, the output voltage at these pins is at VOL. Logic Input of the Complementary Level Shifters. While the corresponding input voltage of these level shifters is below the threshold voltage, the voltage at the noninverting output pins is at VOH and the voltage at the inverting outputs is at VOL. While the corresponding input voltage of these level shifters is above the threshold voltage, the voltage at the noninverting output pins is at VOL and the voltage at the inverting outputs is at VOH.
Rev. 0 | Page 10 of 24
AD8385 BLOCK DIAGRAMS AND TIMING DIAGRAMS
DECDRIVER SECTION
DB(0:9)
10
10
10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH
DAC
VID0
AD8385
DAC
VID2
DAC
VID4
BYP
BIAS 10 2-STAGE 10 LATCH DAC VID6
CLK STSQ XFR R/L
SEQUENCE CONTROL
10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH 10 2-STAGE 10 LATCH
DAC
VID8
DAC
VID10
DAC
VID1
DAC
VID3
DAC
VID5
DAC
VID7
DAC
VID9
DAC
VID11
INV
INV CONTROL
04514-0-004
SCALING CONTROL VRH VRL V1 V2
Figure 4. Block Diagram
Rev. 0 | Page 11 of 24
AD8385
tr
CLK
tr t8 t7
VTH
t1
DB(0:9)
t2
t1
t2
VTH
STSQ
t3
t4
VTH
XFR
VTH
t5
t6
Figure 5. Input Timing
CLK
DB(0:9) STSQ XFR INV V2+VFS VID(0:11) V2
-9 -8 -7 -6 -5 -4 -3 -2 -1 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
50%
t9 t27 MAX
PIXELS -12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1 PIXELS 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
V1-VFS
Figure 6. Output Timing (R/L = Low)
Table 9.
Parameter t1 Data Setup Time t2 Data Hold Time t3 STSQ Setup Time t4 STSQ Hold Time t5 XFR Setup Time t6 XFR Hold Time t7 CLK High Time t8 CLK Low Time t9 Data Switching Delay t10 Invert Switching Delay t27 INV to CLK Setup Time Conditions Input tr, tf = 2 ns Min 0 3 0 3 0 3 3 2.5 10 13 0.5/fCLK Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns
12 15
14 17 5.5/fCLK
Rev. 0 | Page 12 of 24
04514-0-006
t27 MIN
t9 t10
V1
04514-0-005
AD8385
LEVEL SHIFTERS
DYIN DXIN DIRYIN DIRXIN NRGIN ENBX1I ENBX2I ENBX3I ENBX4I DY DX DIRY DIRX NRG ENBX1 ENBX2 ENBX3 ENBX4
CLXN CLYN
04514-0-007
Figure 8. Level Shifter--Complementary
Figure 7. Level Shifter--Inverting
INPUTS
t11
INVERTING OUTPUTS
t12
t15 t17
NONINVERTING OUTPUTS
t16 t18
t13
t14
Figure 9. Inverting and Complementary Level Shifter Timing
Table 10. Level Shifter Timing
Parameter Output Rise, Fall Times, tr, tf DX, CLX, CLXN, ENBX[1-4] DY, CLY, CLYN DIRX, DIRY NRG Propagation Delay Times--t11, t12, t13, t14 DX, CLX, CLXN, ENBX[1-4] DY, CLY, CLYN DIRX, DIRY NRG Propagation Delay Skew--t15, t16, t17, t18 ENBX[1-4]--t15, t16 DX to ENBX[1-4]--t16 DX to CLX--t15, t16, t17, t18 DY, CLY, CLYN--t15, t16, t17, t18 Conditions TA MIN to TA MAX CL = 40 pF Min Typ 18.5 40 102 43 61 20 29 70 30 37 Max 30 70 200 50 100 50 50 100 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
CL = 200 pF CL = 300 pF TA MIN to TA MAX CL = 40 pF
CL = 200 pF CL = 300 pF TA MIN to TA MAX, CL = 40 pF
04514-0-009
2 2 10 20
Rev. 0 | Page 13 of 24
04514-0-008
CLXIN CLYIN
CLX CLY
AD8385
LEVEL SHIFTING EDGE DETECTOR
R MONITI S MONITO
04514-0-010
Figure 10. Level Shifting Edge Detector Block Diagram
AVCC MONITI AGND VOH
04514-0-011
t19
t20
MONITO VOL
Figure 11. Level Shifting Edge Detector Timing
Table 11. Level Shifting Edge Detector, AVCC = 15.5 V, DVCC = 3.3 V, CL = 10 pF, TA MIN = 25C, TA MAX = 85C
Parameter VIL VIH VTH LH VTH HL VOH VOL IIH IIL t19 t19 t20 t20 tr tf Input Low Voltage Input High Voltage Input Rising Edge Threshold Voltage Input Falling Edge Threshold Voltage Output High Voltage Output Low Voltage Input Current High State Input Current Low State Input Rising Edge Propagation Delay Time t19 Variation with Temperature Input Falling Edge Propagation Delay Time t20 Variation with Temperature Output Rise Time Output Fall Time Min AGND AVCC - 0.7 Typ Max AGND + 0.75 AVCC Unit V V V V V V A A ns ns ns ns ns ns
-2.5
AGND + 1 AVCC - 1 DVCC - 0.25 0.25 1.2 -1.2 16 2 12 2 5 6
2.5
Rev. 0 | Page 14 of 24
AD8385
SERIAL INTERFACE
SVRH SVRL SDI SCL SEN SD(0:7) SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11
12-BIT SHIFT REGISTER 8
VAO1, VAO2 = SVRL + SDICODE (SVRH-SVRL)/256 DUAL SDAC
/
SELECT LOAD
AO2 AO1
CONTROL
ENABLE THERMAL SWITCH
VIDEO DACs
12
/
12
/
6
/
VID(0:11)
Figure 12. Serial Interface Block Diagram
SEN
SEN
SCL
t20
SCL
SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
04514-0-013
t21 t24 t25
t22
t23
VAO1, VAO2
SDI
D11
D10
D1
D0
VAO1, VAO2
t26
Figure 14. Serial Interface Timing
Table 12. Serial DAC Timing
Parameter SEN to SCL Setup Time, t20 SCL, High Level Pulse Width, t21 SCL, Low Level Pulse Width, t22 SDI Setup Time, t24 SDI Hold Time, t25 SCL to SEN Hold Time, t23 VAO1, VAO2 Settling Time, t26 Conditions Min 10 10 10 10 10 10 Typ Max Unit ns ns ns ns ns ns ms ms
VFS = 5 V, to 0.5%, CL = 100 pF VFS = 5 V, to 0.5%, CL = 33 F
1
2 15
Rev. 0 | Page 15 of 24
04514-0-014
Figure 13. Serial Interface Timing
04514-0-012
TSTM
AD8385 FUNCTIONAL DESCRIPTION
The AD8385 is a system building block designed to directly drive the columns of LCD microdisplays of the type popularized for use in projection systems. It comprises 12 channels of precision, 10-bit digital-to-analog converters loaded from a single, high speed, 10-bit wide input. Precision current feedback amplifiers, providing well-damped pulse response and fast voltage settling into large capacitive loads, buffer the 12 outputs. Laser trimming at the wafer level ensures low absolute output errors and tight channel-to-channel matching. Tight part-topart matching in high resolution systems is guaranteed by the use of external voltage references. Three groups of level shifters convert digital inputs to high voltage outputs for direct connection to the control inputs of LCD panels. An edge detector conditions a high voltage reference timing input from the LCD and converts it to digital levels for use in synchronizing timing controllers, such as the AD8389.
INV Control--Analog Output Inversion
The analog voltage equivalent of the input code is subtracted from (V2 + VFS) while INV is held high and added to (V1 - VFS) while INV is held low. Video inversion is delayed by 6 to 12 CLK cycles from the INV input.
TSTM Control--Test Mode
A low on this input allows serial interface control of the output operating mode and the thermal switch. A high on this input turns the thermal switch on and releases the video outputs and VAO1 from grounded mode.
3-Wire Serial Interface--SDAC, Output, Thermal Switch Control
The serial interface controls two 8-bit serial DACs, the thermal switch of the overload protection circuit, and the video output operating mode via a 12-bit-wide serial word from a microprocessor. Four of the 12 bits select the function; the remaining 8 bits are the data for the serial DACs. Table 13. Bit Definitions
Bit Name SD(0:7) SD8 SD9 SD10 SD11 Bit Functionality 8-bit SDAC data. MSB = SD7 Not used Thermal switch control Output operating mode, SDAC selection, and thermal switch control Output operating mode and SDAC selection control
REFERENCE AND CONTROL INPUT
Start Sequence Control--Input Data Loading
A valid STSQ control input initiates a new 6-clock loading cycle during which 12 input data-words are loaded sequentially into 12 internal channels. Data is loaded on both the rising and falling edges of CLK. A new loading sequence begins on the current rising CLK edge only when STSQ is held high at the preceding rising CLK edge.
Right/Left Control--Input Data Loading
To facilitate image mirroring, the direction of the loading sequence is set by the R/L control. A new loading sequence begins at Channel 0 and proceeds to Channel 11 when the R/L control is held low. It begins at Channel 11 and proceeds to Channel 0 when the R/L control is held high.
Table 14. Truth Table @ TSTM = Low
SEN 11 0 1 SD 10 9 0X 0X 8 X X Action Load VAO2. No change to VAO1. Load VAO1. Release video outputs from grounded mode. No change to VAO2. Release video outputs and VAO1 from grounded mode. Disable thermal switch. No change to VAO1 and VAO2. Release video outputs and VAO1 from grounded mode. Enable thermal switch. No change to VAO1 and VAO2. Video outputs and VAO1 to grounded output mode. Disable thermal switch. No change to VAO1, VAO2. Video outputs and VAO1 to grounded output mode. Enable thermal switch. No change to VAO1, VAO2. Start a serial interface loading cycle. No change to outputs.
XFR Control--Data Transfer to Outputs
Data transfer to the outputs is initiated by the XFR control. Data is transferred to all outputs simultaneously on the rising CLK edge only when XFR is high during the preceding rising CLK edge.
0
1
0
X
0
1
1
X
V1, V2 Inputs--Voltage Reference Inputs
Two external analog voltage references set the levels of the outputs. V1 sets the output voltage at Code 1023 while the INV input is low, and V2 sets the output voltage at Code 1023 while the INV input is held high.
1 1 0 X
1
1
1
X
VRH, VRL Inputs--Full-Scale Video Reference Inputs
Twice the difference between these analog input voltages sets the full-scale output voltage VFS = 2 (VRH-VRL).
X X X X
Rev. 0 | Page 16 of 24
AD8385
Table 15. Truth Table @ TSTM = High. Thermal Switch Enabled. Grounded Output Disabled.
SEN 11 0 1 X X
X = Don't Care.
SD 10 9 0 0 1 X X X X X
8 X X X X
Action Load VAO2. No change to VAO1. Load VAO1. No change to VAO2. No change to VAO1 and VAO2 data. Start a serial interface loading cycle. No change to outputs.
For systems that operate at high internal ambient temperatures and require large capacitive loads to be driven by the AD8385 at high frequencies, junction temperatures above 125C may be required. In such systems, the thermal switch should either be disabled or a minimum airflow of 200 lfm be maintained.
SERIAL DACS
Both serial DACs are loaded via the serial interface. The output voltage is determined by the following equation: VAO1, VAO2 = SVRL + SD(0:7) x (SVRH - SVRL)/256 Output VAO1 is designed to drive very large capacitive loads, above 0.047 F. Lower capacitive loads may result in excessive overshoot at VAO1.
OUTPUT OPERATING MODE
In normal operating mode, the voltage of the video outputs and VAO1 is determined by the inputs. In grounded output mode, the video outputs and VAO1 are forced to (AGND + 0.1 V) typ.
Level Shifters
The characteristics of the level shifters are optimized based on their intended use. Seven level shifters--DX, CLX, CLXN, and ENBX[1:4]--are optimized for the X direction and three--DY, CLY and CLYN-- are optimized for the Y direction control signals. One level shifter--NRG--is designed to drive a large capacitive load and is optimized for an X direction control signal. Two level shifters--DIRX and DIRY--are optimized for very low frequency control signals. One level shifting edge detector--MONITI, MONITO--is optimized to condition a synchronizing feedback reference signal from the LCD.
OVERLOAD PROTECTION
The overload protection employs current limiters and a thermal switch to protect the video output pins against accidental shorts between any video output pin and AVCC or AGND. The junction temperature trip point of the thermal switch is 165C. Production test guarantees a minimum junction temperature trip point of 125C. Consequently, the operating junction temperature should not be allowed to rise above 125C with the thermal switch enabled.
Rev. 0 | Page 17 of 24
AD8385 THEORY OF OPERATION
TRANSFER FUNCTION AND ANALOG OUTPUT VOLTAGE
The DECDRIVER has two regions of operation where the video output voltages are either above reference voltage V2 or below reference voltage V1. The transfer function defines the video output voltage as the function of the digital input code: VIDx(n) = V2 + VFS x (1 - n/1023), for INV = high VIDx(n) = V1 - VFS x (1 - n/1023), for INV = low where: n = input code VFS = 2 x (VRH - VRL) A number of internal limits define the usable range of the video output voltages, VIDx. See Figure 15.
ACCURACY
To best correlate transfer function errors to image artifacts, the overall accuracy of the DECDRIVER is defined by two parameters, VDE and VCME. VDE, the differential error voltage, measures the difference between the rms value of the output and the rms value of the ideal. The defining expression is [VOUTN(n) - V 2] - [VOUTP(n) - V 1] n - 1 - VDE(n) = x VFS 2 1023 VCME, the common-mode error voltage, measures 1/2 the dc bias of the output. The defining expression is
11 V1 + V 2 VCME(n) = (VOUTN(n) +VOUTP(n)) - 2 2 2
AVCC 1.3V
V2 + VFS
INV = HIGH VOUTN(n) V2 5V V2 (AVCC - 4) V1 VOUTP(n) INV = LOW 0 VFS 5.5V 5V V1 (AVCC - 4) 1.3V AGND 0 INPUT CODE 1023
INTERNAL LIMITS AND USABLE VOLTAGE RANGES
0 VFS 5.5V
9V AVCC 18V
V1 - VFS
04514-0-015
VIDx (V)
Figure 15. Transfer Function and Usable Voltage Ranges
Rev. 0 | Page 18 of 24
AD8385 APPLICATIONS
AD8385
DB(0:9) VID(0:11) 12-CHANNEL LCD CHANNEL 0-5
STSQ, XFR, CLK, R/L, INV
IMAGE PROCESSOR
DIRXIN, DIRYIN, DYIN, CLYIN, NRGIN
DIRX, DIRY, DY, CLY, CLYN, NRG
LCD TIMING CONTROLS
1/3 AD8389
DXI, CLXI, ENBX(1-4)I DXxO, CLXxO, ENBX(1-4)xO MONITxI DXIN, CLXIN, ENBXIN (1-4) MONITO DX, CLX, CLXN, ENBX (1-4) MONITI VAO1 VAO2 LCD TIMING CONTROLS
CLK
MONITOR VCOM
SDI P SCL SEN VRH, VRL, V1, V2, SVRH, SVRL
DC REFERENCE VOLTAGES
Figure 16. Typical Applications Circuit
OPTIMIZED RELIABILITY WITH THE THERMAL SWITCH
While internal current limiters provide short-term protection against temporary shorts at the outputs, the thermal switch must be enabled to protect against persistent shorts lasting for several seconds.
OPTION A OPTION B
DVCC
DVCC
AD8385
SERVICE JUMPER TSTM PIN7
04514-0-016
Initial Power-Up After Assembly or Repair Using a Service Jumper
To optimize reliability with the use of the thermal switch, the following sequence of operations is recommended: 1. 2. 3. 4. 5. 6. Ensure that the TSTM pin is high on initial power-up by inserting a service jumper. See Figure 17. Execute the initial power-up. Identify any shorts at outputs. Power down, repair shorts, and repeat the initial power-up sequence until proper system functionality is verified. Remove service jumper. Resume normal operation.
SERVICE JUMPER TO P
AD8385
TSTM PIN7
DGND
Figure 17. Service Jumper Location
Initial Power-Up after Assembly or Repair Using the Serial Interface
1. Immediately after power-up, send Code 011XXXXXXXXX through the serial interface to enable the thermal switch and disable the grounded output mode. Identify any shorts at the outputs. Power down, repair shorts, and repeat the initial power-up sequence until proper system functionality is verified. Resume normal operation.
2. 3. 4.
Rev. 0 | Page 19 of 24
04514-0-017
AD8385
Power-Up During Normal Operation
The serial interface has no power-on reset. Code 010XXXXXXXXX, sent immediately following a power-up places, all outputs into normal operating mode and disables the thermal switch.
Internal Bias Voltage Generation
Standard systems that internally generate the bias voltage reserve the uppermost code range for the bias voltage, and use the remaining code range to encode the video for gamma correction. A high degree of ac symmetry is guaranteed by the AD8385 in these systems. The V1 and V2 inputs in these systems are tied together and are normally connected to VCOM, as shown in Figure 18.
OPERATION IN HIGH AMBIENT TEMPERATURE
To extend the maximum operating junction temperature of the AD8385 to 150C, keep the thermal switch disabled during normal operation. Code format X10XXXXXXXXX ensures a disabled thermal switch.
POWER SUPPLY SEQUENCING
As indicated in the Absolute Maximum Ratings, the voltage at any input pin cannot exceed its supply voltage by more than 0.5 V. To ensure compliance with the Absolute Maximum Ratings, the following power-up and power-down sequencing is recommended. During power-up, initial application of nonzero voltages to any of the input pins must be delayed until the supply voltage ramps up to its highest operational input voltage. During power-down, the voltage at any input pin must reach zero during a period not exceeding the hold-up time of the power supply. Failure to comply with the Absolute Maximum Ratings, may result in functional failure or damage to the internal ESD diodes. Damaged ESD diodes can cause temporary parametric failures, which can result in image artifacts. Damaged ESD diodes cannot provide full ESD protection, reducing reliability. Table 16.
Power-On 1. Apply power to supplies. 2. Apply power to other I/Os. Power-Off 1. Remove power from I/Os. 2. Remove power from supplies.
AD8385
VCOM V2 V1 VCOM
VFS = 5V
VBIAS = 1V VBIAS = 1V 820 1023
VFS = 5V
Figure 18. V1, V2 Connection and Transfer Function in a Typical Standard System
External Bias Voltage Generation
In systems that require improved brightness resolution and higher accuracy, the V1 and V2 inputs, connected to external voltage references, provide the necessary bias voltage (VBIAS) while allowing the full code range to be used for gamma correction. To ensure a symmetrical ac voltage at the AD8385's outputs, VBIAS must remain constant for both states of INV. Therefore, V1 and V2 are defined as V1 = VCOM - VBIAS V2 = VCOM + VBIAS
VBIAS GENERATION--V1, V2 INPUT PIN FUNCTIONALITY
To avoid image flicker, a symmetrical ac voltage is required and a bias voltage of approximately 1 V minimum must be maintained across the pixels of HTPS LCDs. The AD8385 provides an internal and external method of maintaining this bias voltage.
Rev. 0 | Page 20 of 24
04514-0-018
RESERVED CODE RANGE
AD8385
APPLICATIONS CIRCUIT
The following circuit ensures VBIAS symmetry to within 1 mV with a minimum component count. Bypass capacitors are not shown for clarity.
AVCC = 15.5V
PCB DESIGN FOR OPTIMIZED THERMAL PERFORMANCE
The total maximum power dissipation of the AD8385 is partly load-dependent. In a 12-channel 60 Hz XGA system running at a 65 MHz pixel rate, the total maximum power dissipation is 2.3 W at an LCD channel input capacitance of 150 pF. At a 100 MHz pixel rate, the total maximum power dissipation can exceed 3 W. To limit the operating junction temperature at or below the guaranteed maximum, the package, in conjunction with the PCB, must effectively conduct heat away from the junction. The AD8385 package is designed to provide enhanced thermal characteristics through the exposed die paddle on the bottom surface of the package. To take full advantage of this feature, the exposed paddle must be in direct thermal contact with the PCB, which then serves as a heat sink. A thermally effective PCB must incorporate two thermal pads and a thermal via structure. The thermal pad on the top PCB layer provides a solderable contact surface on the top surface of the PCB. The thermal pad on the bottom PCB layer provides a surface in direct contact with the ambient. The thermal via structure provides a thermal path to the inner and bottom layers of the PCB to remove heat.
VZ = 5.1V
1 VCOM = 7V R2 = 1k
3 -IN V+ 5 V2 = 8V
AD8385
V2
2V OCM AD8132 8 +IN V- 6 4 V1 = 6V V1
04514-0-019
R1 = 6k DVCC = 3.3V
Figure 19. External VBIAS Generator with the AD8132
VFS = 4V V2 VCOM V1 VFS = 4V
04514-0-020
VBIAS = 1V VBIAS = 1V 1023
THERMAL PAD DESIGN
To minimize thermal performance degradation of production PCBs, the contact area between the thermal pad and the PCB should be maximized. Therefore, the size of the thermal pad on the top PCB layer should match the exposed paddle size. The second thermal pad of at least the same size should be placed on the bottom side of the PCB. At least one thermal pad should be in direct thermal contact with a plane such as AVCC or GND.
Figure 20. AD8385 Transfer Function in a Typical High Accuracy System
8.75 7.50 6.25 5.00
THERMAL VIA STRUCTURE DESIGN
TA = 85C TA = 25C
(V2 + V1)/2 - VCOM (mV)
3.75 2.50 1.25 0.00 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 5.7 6.2 6.7 7.2 7.7 8.2 8.7 9.2 9.7 10.2 10.7
04514-0-021
Effective heat transfer from the top to the inner and bottom layers of the PCB requires thermal vias incorporated into the thermal pad design. Thermal performance increases logarithmically with the number of vias. Near optimal thermal performance of production PCBs is attained only when tightly spaced thermal vias are placed on the full extent of the thermal pad.
-8.75 (V+) - (V-) (V)
Figure 21. Typical Asymmetry at the Outputs of the AD8132 vs. Its Power Supply for the Application Circuit
Figure 21 shows that the AD8132 (Figure 19) typically produces a symmetrical output at 85C when its supply, (V+) - (V-), is at 7.2 V.
Rev. 0 | Page 21 of 24
AD8385
AD8385 PCB DESIGN RECOMMENDATIONS
Top PCB Layer
* * * * Pad size: 0.25 mm x 0.25 mm
6.5 mm 16 mm
Pad pitch: 0.5 mm
16 mm
Thermal pad size: 6.5 mm x 6.5 mm Thermal via structure: 0.25 mm diameter vias on a 0.5 mm grid
6.5 mm
Bottom PCB Layer
It is recommended that the bottom thermal pad be thermally connected to a plane. The connection should be direct such that the thermal pad becomes part of the plane.
Figure 22. Land Pattern--Top Layer
04514-0-022
The use of thermal spokes is not recommended when connecting the thermal pads or via structure to the AVCC plane.
Solder Masking
To minimize the formation of solder voids due to solder flowing into the via holes (solder wicking), the via diameter should be small. Optional solder masking of the via holes on the top layer of the PCB plugs the via holes, inhibiting solder flow into the holes. To optimize the thermal pad coverage, the solder mask diameter should be no more than 0.1 mm larger than the via hole diameter.
6.5 mm
6.5 mm
Solder Mask--Top Layer
04514-0-023
* *
Pads: Set by the customer's PCB design rules Thermal vias: 0.25 mm diameter circular mask, centered on the vias.
Figure 23. Land Pattern--Bottom Layer
Solder Mask--Bottom Layer
Set by the customer's PCB design rules.
Figure 24. Solder Mask--Top Layer
Rev. 0 | Page 22 of 24
04514-0-024
AD8385 OUTLINE DIMENSIONS
Figure 25. 100-Lead, Thermally Enhanced Thin Quad Flat Package (with Exposed Heat Sink) [TQFP_EP] (SV-100-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8385ASVZ1 Temperature Range 0C to 85C Package Description 100-Lead TQFP_EP Package Option SV-100-3
1
Z = Pb-free part.
Rev. 0 | Page 23 of 24
AD8385 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04514-0-1/05(0)
Rev. 0 | Page 24 of 24

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